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    • 专利摘要:
    The invention relates to a read circuit structure, constituted on a semiconductor substrate (1) of a first type, and for measuring the charges received from a charge source (2) external to the substrate (1) according to the invention. successive cycles of integration of charges, said structure comprising: an injection diode formed configured to inject into the substrate (1) the charges received from the external charge source (2), a collection diode able to collect in the substrate (1) at least a portion of the charges injected by the injection diode and accumulating these charges during an integration cycle, • a charge recovery structure (7), configured to recover the charges accumulated in said collection diode; means for initializing the charge recovery structure (7) at the end of each integration cycle, by bringing the electrical potential of said charge recovery structure back to a potent initial iel.
    公开号:FR3022425A1
    申请号:FR1455361
    申请日:2014-06-12
    公开日:2015-12-18
    发明作者:Yang Ni
    申请人:New Imaging Technologies SAS；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The invention relates to a read circuit structure for an electromagnetic sensor. By "electromagnetic sensor" is meant in this text an electromagnetic radiation sensor composed of pixel reading circuits, each pixel comprising at least one photodiode for emitting an electrical signal representative of the radiation to which the pixel is exposed. Such a sensor is made from a semiconductor substrate (for example made of silicon) in which the photodiodes are constituted. The radiation that one seeks to exploit may for example be a radiation in the visible spectrum, however this is not limiting.
    [0002] The electrical signal emitted by each photodiode is read by a read circuit (generally a respective read circuit is dedicated to each photodiode for this purpose). The reading circuits are also constituted in the silicon semiconductor substrate. The invention finds an advantageous application in hybrid sensors.
    [0003] A sensor is said to be "hybrid" when the photodiodes are constituted in a first distinct substrate of a second substrate which integrates the reading circuits and whose semiconductor material may differ from the material of the first substrate. This is particularly the case when the reading circuits are constituted in a silicon substrate (which corresponds to the most common configuration for these read circuits), whereas the photodiodes are often constituted in a substrate in another material, for example gallium-indium arsenide (InGaAs), which makes it possible to constitute photodiodes sensitive to wavelengths adapted to night vision, to which a photodiode in a silicon substrate is not sensitive.
    [0004] In the case of a hybrid sensor, each photodiode of the first substrate is connected to a reading circuit of the second substrate by a weld type connection, for example an indium ball. Figures la and lb show examples of possible configurations of this hybridization, according to the technique of flip chip (- flip chip "in English). According to this technique, the face 31 of the first substrate 32 at which the photodiodes 33 are formed, and the face 34 of the second substrate 35 at which the reading circuit 36 is made, face each other. In a first example illustrated by FIG. 1a, each of the photodiodes 33 of the first substrate 32 is connected to the reading circuit 36 by an indium ball 37, while in the second example illustrated by FIG. 1b, the connection is made by a copper pillar 38 starting from the second substrate 35 and by a solder 39 between this pillar 38 and the photodiode 33. BACKGROUND OF THE INVENTION Reading signals from the photodiodes is performed at a given frequency, which is generally the same frequency for all the photodiodes. For example for video applications the frequency can be 50 or 60 Hertz. For fast or fast acquisition applications, the frequency is higher.
    [0005] The reading of the photodiodes is thus done by "cycles", each cycle corresponding to the integration time of the pixel, that is to say the time during which the electric charge (constituted by the charges of the electrons or holes, according to the nature of the photodiode) generated by the photodiode is accumulated either in the photodiode or in the reading circuit, as well as in the reading time of the pixel.
    [0006] The reading circuit of the photodiode can be realized in different ways, in a CMOS technology. It can be especially of the "direct injection" (DI for Direct Injection) type, "capacitive transimpedance amplification" (CTIA for "Capacitive Trans-Innpedance Amplifier" in English), or "source follower per pixel" (SFP for "Source Follower per Pixel" in English). These three types of reading circuits are illustrated in FIGS. 2a to 2c. FIG. 2a illustrates an exemplary electrical diagram of a direct injection type pixel reading circuit in a hybrid configuration. An amplifier 23 associated with a transistor 22 stabilizes the bias voltage applied to the photodiode 20 via the hybridization contact 21 between the first substrate on which the photodiode 20 is made and the second substrate on which the reading circuit is made. An initialization transistor 24 is controlled by an initialization signal RST in order to apply an initialization voltage VRsT at the output of the transistor 22. An integration capacitor 25 is adapted to integrate the photo-current emitted by the photodiode 20. A buffer amplifier 26 makes it possible to send the signal voltage IM at the terminals of this integration capacitor 25 to a scanning multiplexing bus 28, via a selection switch 27. A read cycle comprises: 1) initialization of the integration capacitor 25 by means of the initialization transistor 24, 2) integration in the capacitor 25 of the photoelectric charges generated by said photodiode 20, 3 ) reading of the IM signal voltage across the capacitor 25 via the control of the switch 27.
    [0007] The result of the reading can either be output directly from the reading circuit to be exploited, or be stored in a memory present in each pixel for later use. The reset of the integration capacitor 25 and the photodiode 20, however, produces an electronic noise called "KTC", K denoting the Boltzmann constant, T the temperature in Kelvin and C the capacitance of the integration capacitor 25, with reference to the magnitudes influencing this sound. After the initialization, the residual charge in the integration capacitor 25 has a random variation whose root mean square is equal. Thus, this KTC noise results in an error of deviation of the voltage at the terminals of the integration capacitor 25 with respect to the reset voltage VRsT. In order to suppress this switching noise, a strategy has been developed combining two voltage readings at the output of the pixel: it is thus a correlated double reading, also known as CDS (for Correlated Double Sarnpling ").
    [0008] A first reading is performed at the beginning of the cycle, immediately after the capacitor has been restored to an initial state (reset or `reset 'in English - a term sometimes used for convenience and which must be considered equivalent), by a setting to a reference potential. This first reading gives a first read value of the amount of initial charges in the capacitor. The second reading is performed at the end of the cycle, when the capacitor is charged and it is desired to read the value of the cumulative integrated charges. Once the two readings have been carried out and the cycle ends, comparison and calculation means establish the difference between the two read values. This difference gives the amount of charge generated by the photodiode that has been integrated by the capacitor during the integration time. These circuits and methods of known types thus make it possible to determine, by calculating the difference between a cycle start reading and an end of cycle reading, for each photodiode and for each cycle, a value of the quantity of charges integrated into the circuit. capacitor from the photodiode during the integration cycle. However, other sources of noise exist in a photodiode reading circuit. However, for most of these noises, there is no correlation between the first reading and the second reading. Thus, not only these other noises are not suppressed, but in addition their spectral power density is increased by a factor of 2. For a reading circuit CMOS (English Connective Metal Oxide Senniconductor) an electronic noise said 1 / f is the dominant noise in all active components such as transistors. The power spectral density of this 1 / f noise decreases with frequency. Thus, at low frequency, the noise 1 / f is important. However, the frequency of the pixel operating cycles is of the order of 50 Hz, which results in a significant noise 1 / f which limits the effectiveness of the correlated double-reading.
    [0009] In order to reduce the noise 1 / f compared to the direct injection, another type of circuit called CTIA, of the English - Capacitive Trans-innpedance Amplifier "for capacitive transimpedance amplifier, a schematic example of which is illustrated by Figure 2b. The principle is similar to that of a direct injection circuit, with similar elements designated by the same reference numerals. The photocurrent from the photodiode 20 is integrated in the capacitor 25 through an operational amplifier 29 provided with a capacitive feedback. The initialization is done by emptying the charges in the capacitor 25 by means of the initialization transistor 24 connected in parallel. The bias voltage of the photodiode 20 is maintained thanks to the high gain of the operational amplifier 29. The basic principle of this configuration is that the capacitive feedback reduces the low frequency noise and the efficiency of the double reading correlated is thus improved. The reading sequence is the same as that of a direct injection pixel: a first reading is made after the reset and a second reading is made after the integration time, the image signal being constituted by the difference between these two readings. Despite the complexity of the pixel, the noise 1 / f remains important. In fact, the best CTIA reading circuits can not fall below a noise level corresponding to the charge of 40 to 50 electrons, for a very low capacitance value (5 to 10 fF). In such a configuration, the dynamics of the circuit is very low, and it saturates easily when the light exposure becomes too great. Another configuration called SFP, Source Follower per Pixel, source follower per pixel, of which Figure 2c shows an exemplary embodiment. This configuration aims to reduce the number of transistors to reduce the number of sources of noise 1 / f. The operating cycle is the same as a pixel read circuit Di or CTIA, and the elements similar to these circuits are designated by the same reference numerals. In an SFP pixel readout circuit, integration of the photo-current from the photodiode 20 is performed directly on the photodiode integration capacitor 25, including some parasitic capacitances. The high capacitive value of the photodiode 20 reduces the amplitude of the signal read in voltage. The noise of the reading circuit finally limits the level of noise reported to the photodiode 20 as the number of electrons. For example, a CTIA pixel reading circuit can operate with a capacitance of 5 fF for the integrating capacitor, and for a reading noise of 320 pV amplitude, the noise level is thus equivalent to the electric charge. of 10 electrons. In an SFP pixel readout circuit, the integration capability can hardly be less than 20 fF. In this case, the 320 pV read noise results in a noise equivalent to 40 electrons.
    [0010] Another drawback for the correlated double reading in each of these circuits is that the first reading takes place at the beginning of the integration cycle, while the second reading takes place at the end of it. The two readings are separated by a long enough time, comparable to the cycle time. The time separating the two readings of each cycle corresponds to the integration time, which is equal to the cycle time (to the reset time). However, between these two readings other electronic noise than the KTC noise can disturb the measurement, like the noise 1 / f, which can thus, by its variations between the two readings, lead to values of loads (deduced from the difference of the two values read) erroneous. This is penalizing and will be even more so as the cycle time is long, corresponding to low frequencies. By way of illustration, an application which is particularly penalized by this limitation is low-level vision of light, which requires long cycle times, with frequencies of the order of 50 Hz. Another limitation of these known circuits and methods is that they require to memorize in a memory the value read at the beginning of cycle, to then carry out the operation of comparison and subtraction at the end of cycle. Therefore, a memory, for example external or on the contrary in each pixel reading circuit, is therefore necessary to store the first reading during the integration time.
    [0011] PRESENTATION OF THE INVENTION The invention aims to overcome these limitations and disadvantages. For this purpose, a reading circuit structure is proposed, constituted on a semiconductor substrate of a first type, and intended to measure the charges received from a source of charges external to the substrate according to successive cycles of integration. charge unit, said structure comprising: - an injection diode formed in the substrate by a first PN junction comprising a first doped region of a second type of the substrate for receiving electrical charges from said external charge source, and configured to inject in the substrate the charges received from the external charge source, - a collection diode formed in the substrate by a second PN junction comprising a second doped region of the second type buried in the substrate and able to collect in the substrate at least a part charges injected by the injection diode and accumulating these charges during an integration cycle, - a recovery structure of arges, configured to recover accumulated charges in said collection diode; means for initializing the charge recovery structure at the end of each integration cycle, by bringing the electrical potential of said charge recovery structure to a potential initial. The structure is advantageously completed by the following characteristics, taken alone or in any of their technically possible combinations: the charge recovery structure comprises a floating diffusion node formed by a doped region of the second type in the substrate, connected to a device Release ; the means for initializing the charge recovery structure comprise an initialization transistor whose gate, electrically isolated from the substrate, is situated between said diffusion node and a reference potential source, and is adapted to be controlled to bring the potential of said broadcast node at said initial potential; the structure comprises an MOS transfer transistor whose transfer gate is situated between said buried diode and said floating diffusion node, above and electrically isolated from the substrate, and which is suitable for transferring the charges collected in the second region doped towards the floating diffusion node; the charge recovery structure comprises a memory constituted by a doped region of the second type and a floating diffusion node formed by a doped region of the second type connected to an output device, said memory being formed in the substrate between the buried diode and the floating diffusion node; an output device is connected between the external charge source and the injection diode in order to read the voltage across the injection diode and thus to obtain a logarithmic reading of the current passing between the external charge source and the injection diode; the structure comprises a confinement zone formed by a doped region of the first type formed in the substrate, said confinement zone extending in the depth of the substrate at least opposite the first doped region composing the injection diode; the confinement zone further extends towards the surface of the substrate to the periphery of the injection diode; the structure comprises a doped region of the first type formed in the substrate which surrounds a doped region of the second type of initialization means, said doped region of the second type being connected to a source of reference potential, and said doped region of the first type; type extending to a doped region of the second type belonging to the charge recovery structure; the charge recovery assembly comprises a plurality of second doped regions of the second type buried in the substrate each forming a diode buried with said substrate, able to capture in the substrate at least a portion of the charges injected by an injection diode; common, and to accumulate these charges during a load integration cycle; the injection diode is formed of a plurality of first doped regions of the second type electrically connected to each other; the second doped region of the buried collection diode is configured to be completely depleted at the end of the charge transfer to the charge recovery structure. The invention relates to a method for operating a read circuit structure according to any one of the preceding claims, wherein - a first reading of the voltage at the charge recovery structure is made after initialization of said charge recovery structure and before the transfer of charges from the buried diode to said charge recovery structure, and - a second reading of the voltage at the charge recovery structure is performed after the transfer of charges from the diode buried to said charge recovery structure, the image signal corresponding to the difference between the first reading and the second reading. The invention also relates to a matrix reading circuit comprising a plurality of read circuit structures according to the invention. The invention also relates to a hybrid sensor comprising a first substrate on which is formed a read circuit according to the invention, and a second substrate on which is formed a matrix of elements sensitive to electromagnetic radiation constituting the external charge sources, for example photodiodes. The read circuit and the array of sensitive elements can be connected by a link in a configuration according to the flip-chip technique. PRESENTATION OF THE FIGURES The invention will be better understood, thanks to the following description, which relates to embodiments and variants according to the present invention, given as non-limiting examples and explained with reference to the attached schematic drawings. , in which: - Figures la and 1b, already commented, illustrate examples of possible configurations of hybrid sensor, according to the flip-flop technique; - Figures 2a, 2b and 2c, already commented, illustrate examples of reading circuit of the photodiode in a CMOS technology, belonging to the state of the art; FIG. 3 schematically illustrates a read circuit structure according to a possible embodiment of the invention; - Figure 4 schematically illustrates the operating cycle of the structure of Figure 3; - Figures 5 to 9 schematically illustrate a read circuit structure according to possible embodiments of the invention. In the figures, similar elements are designated by the same reference numerals. DETAILED DESCRIPTION The following description is initially made with reference to a read circuit structure constituted on a P-type semiconductor substrate. However, the invention is not limited to this embodiment which does not only an illustrative character.
    [0012] With reference to FIG. 3, the read circuit structure is formed on a P type semiconductor substrate 1 (P-sub). The substrate 1 has different doped regions constituting elements of the read circuit structure. The active read circuit structure is intended to measure the charges received from a charge source 2 outside the substrate 1. This charge source 2 is a photodiode formed on a second substrate different from the substrate 1 on which the charge structure is made. reading circuit. In particular, this external source of charges 2 can be made on a second substrate as in hybrid configurations of the type illustrated in FIGS. 1a and 1b. The external source of charge 2 could also be a current source of a type other than a photodiode.
    [0013] A PN junction is formed in a first doped region 4 of the substrate 1 to receive electrical charges from the external charge source 2 to the substrate 1. The first doped region 4 of the substrate is N-doped. The charge source 2 is connected to the PN injection junction 4, for example via a hybridization contact 3 formed by a weld type connection, as in the examples of Figures la and 1b. The junction PN thus receives the electric current generated by the external charge source 2 to the substrate 1. The first PN junction is forward biased so as to be able to inject into the substrate 1 the charges received from the charge source 2 outside the substrate 1 The first PN junction thus constitutes a diode for injecting charges into the substrate 1. The injection of the charges into the substrate 1 by the injection diode is represented by arrows in dashed lines in FIG. there will be no distinction made between the diode and the doped region which constitutes with the substrate a PN junction.
    [0014] In the case of a P-type substrate 1 and a N-type first doped region 4, the injected charges are electrons, and the number of free electrons thus injected into the substrate 1 is proportional to the product between the duration injection circuit and the electric current flowing between the photodiode 2 and the first doped region 4. The read circuit structure comprises a second PN junction 20 comprising a second doped region 6 of the second type, buried in the substrate, and forming with the a buried collection diode, able to collect in the substrate 1 at least a portion of the charges injected by the injection diode and to accumulate these charges during a charge integration cycle. The distance between the second doped region 6 and the first doped region 4 is less than the electron diffusion length in the substrate 1 at a nominal use temperature, for example at 20 ° C., and is preferably less than 150 ° C. [Inn. The PN junction formed around this buried second doped region 6 and the depth of penetration of the depletion zone therein depends on the doping and polarization voltage of the second doped region 6. When the depletion zone invades any this second doped region 6, there is no more mobile charges, that is to say more free electrons in the case of a second doped region 6 type N. The only remaining charge in this second region doped 6 is then the fixed charge, positive in the case of a second type N, left by the doping atoms.
    [0015] The second doped region 6 is buried in the substrate 1 so that the space charge area (also called depletion zone) of the junction between said second doped region 6 and the substrate 1 does not reach the surface of the substrate 1 when said doped region 6 is devoid of moving charges.
    [0016] In this respect, a doping surface area 5 of the first type, in this case P, may be provided between the doped region 6 of the buried collection diode and the surface of the substrate 1, in order to prevent the depletion zone reach this surface. The article "Estinnates for Scaling of Pinned Photodiodes" by Alex Krynnski et al., 2005 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors gives further details on this point. Once free of free charges, the potential of the second doped region 6 no longer varies, but can still attract mobile charge carriers, in this case electrons in the case of a second N-doped region. 15 free charge carriers are generated or injected near this second doped region 6, they can be attracted and fixed there. The second doped region 6 can then act as an integrator without any initial residual charge. In the initial state after the charge transfer, the potential at which the second doped region is subjected is maximum, and decreases as the charges injected by the injection diode are collected. Therefore, the second doped region 6 of the second type composing the buried collection diode is configured (via its positioning, its dimensions and the dopant concentrations) to be completely depleted at the end of the charge transfer to the recovery structure. loads. It should be noted further that the completely depleted aspect of the second doped region 6 of the buried collection diode makes it possible to suppress the KTC noise. The read circuit structure also includes a charge recovery structure configured to recover charges accumulated in said collection diode. As in the example illustrated in FIG. 3, this recovery structure 30 may comprise a floating diffusion node 7 formed by an N-type doped region in the substrate 1, connected to an output device 8, said region N-doped dopant having a dopant concentration greater than that of the second N-type doped region 6 forming with the substrate 1 the buried collection diode. The charge recovery structure also comprises an MOS transfer transistor whose transfer gate 9 is located between said buried collection diode and said floating diffusion node 7. The gate 9 is above and electrically isolated from the substrate 1 and can be controlled by a transfer signal TX to transfer the charges that are accumulated in the second doped region 6 of the buried diode to the charge recovery structure, here the floating diffusion node 7. As illustrated by FIG. FIG. 5, the charge recovery structure may also comprise a memory constituted by a doped region 15 of the second type, ie N, formed in the substrate 1 between the buried collection diode and the floating diffusion node 7 connected to the output device 8. This doped region 15 is buried as the second doped region 6, and for this purpose a doping surface area of the first type, ie P , isolates said doped region 15 from the surface of the substrate 1. A transistor gate 16 controlled by a signal T1 can control the transfer of charges from the buried collection diode to the memory, while the gate 9 of the transfer transistor serves to controlling the transfer of charges from the memory to the floating diffusion node 7. It should be noted that the memory has an N-type dopant concentration greater than that of the second doped region 6, but less than that of the floating diffusion node 7, in order to present a potential gradient suitable for allowing the transfer of charges. Several memories may be arranged in a similar manner between the buried collection diode and the floating diffusion node 7 connected to the output device 8. The output device 8, through which the output signal resulting from the reading of the voltage can be transmitted. level of the charge recovery structure, may comprise an amplifier 26 and a selection switch 27 connected to the amplifier 26, said selection switch 27 being selectively controllable to connect the output of the amplifier 26 to a multiplexing bus 28. The read circuit structure also comprises means for initializing the charge recovery structure before the charge transfer, by bringing the electric potential of said charge recovery structure to an initial potential greater than the potential at which the second doped region 6 is completely depleted (called pinning voltage), so that when the gate 9 of the transfer transistor allows the transfer of accumulated charges in the second doped region 6 of the buried diode. Like the example illustrated in FIG. 3, the means for initializing the charge recovery structure may comprise an initialization transistor whose gate 10 is located between the floating diffusion node 7 and a source of potential. reference VDD. The gate 10 is electrically isolated from the substrate and can be controlled to bring the potential of said floating diffusion node 7 to said initial potential.
    [0017] The structure may comprise a doped region 12 of the first type formed in the substrate 1 (P-Well) which surrounds a doped region of the second type 11 of the initialization means of the charge recovery structure. This doped region 11 of the second type is connected to a source of reference potential VDD, and said region 12 of the first type extends to a doped region of the second type 7 belonging to the charge recovery structure, typically the node 7. FIG. 4 illustrates the operation of the read circuit structure in the case where the first type is the type P, and the second type is the type N, as in the example of FIG. At time t0, which corresponds to the end of the previous integration cycle, the charge recovery structure, i.e. floating broadcast node 7, is initialized by means of the initialization signal RST to the high state applied to the gate of the initialization transistor 10. The initialization transistor becomes on and the floating diffusion node 7 is then connected to the reference potential source VDD, thus bringing it to an initial potential. This initial potential has a sufficient level to be able to make a total transfer of the charges collected by the buried collection diode 6 when an electrical channel connects the collection diode to the charge recovery structure. Then, at time t1, the initialization signal RST applied to the gate of the initialization transistor 10 is brought back to a low level, so that the initialization transistor becomes blocking again. At time t2, the transfer signal TX applied to the gate of the transfer transistor 9 is brought to a high level, so as to allow the transfer of the charges accumulated in the second doped region 6 of the buried diode to the structure of the charge recovery constituted by the floating diffusion node 7, by the establishment of an electrical channel in the substrate underlying the gate of the transfer transistor 9. The charges collected in the second doped region 6 of the collection diode are then transferred to the floating diffusion node 7 in full, so that the second doped region 6 is completely depleted at the end of this transfer. As indicated above, the depletion zone of the PN junction of the buried diode completely covers the second doped region 6. The potential at this level then corresponds to the so-called "pinning voltage" potential, which depends on the configuration of the dopants . At time t3, the transfer signal TX applied to the gate of the transfer transistor 9 is brought to a low level so as to block the transfer transistor. A new cycle can then begin, whose instants to ', t1', t2 'and t3' respectively correspond to the moments to, t1, t2 and t3. A first reading of the signal via the output device 8 is made between times t1 and t2, and a second reading is made after t3. The first reading informs about the reset level, that is to say the initial level of potential reached by the charge recovery structure after initialization. The integration time, that is to say the collection of the charges injected by the buried collection diode 6, corresponds to the interval between the instants t3 and ty. The voltage difference between the first reading and the second reading gives the desired image signal. It should be noted that the intervals between the instants to and t1, as well as between the instants t2 to t3, are very short, of the order of a few nanoseconds to a few microseconds at the most, while the integration time is the order of a few nnilliseconds. It can therefore be seen that the charge transfer operation allows correlated double readings very close in time, since the first reading and the second reading take place respectively before and after the charge transfer, and are not separated by the time of the transfer. integration as in the configurations of the state of the art previously exposed. The influence of noise 1 / f is reduced compared to these configurations.
    [0018] FIG. 6 shows a reading circuit structure similar to that of FIG. 3, with however the presence of a confinement zone 13 formed by a doped region of the first type formed in the substrate 1, said confinement zone 13 being extending in the depth of the substrate 1 at least opposite the first doped region 4 of the injection diode. As illustrated, the confinement zone 13 may further extend toward the surface of the substrate 1 to the periphery of the injection diode. This confinement zone 13 makes it possible to confine the charges injected by the injection diode into a region of the substrate 1 in which these charges are likely to be attracted by the buried diode. In the case illustrated in FIG. 4, this confinement zone 13 corresponds to a deep P (-P-Well ™) well which nevertheless leaves a region of the substrate 1 free between the injection diode and the buried diode. FIG. 7 shows another configuration, in which the charge recovery assembly 5 comprises a plurality of second doped regions 6 of the second type buried in the substrate 1 each forming a diode buried with said substrate, able to capture in the substrate at less a portion of the charges injected by the common injection diode, and to accumulate these charges during a charge integration cycle. These buried diodes 6 in the substrate 1 are distributed around the injection diode 4, in different directions with respect to said injection diode. Thus, insofar as the charges injected by the injection diode 4 can be collected in the different directions in which these buried diodes 6 are disposed, there are fewer losses, and the collection of the injected charges is thereby improved.
    [0019] In order to further improve the injection and the collection of charges in the substrate 1, the injection diode 4 may be formed of a plurality of first doped regions of the second type electrically connected to each other. Preferably, each of these first doped regions being situated close to at least one buried collection diode 6, that is to say at a distance less than the diffusion length of the electrons in the substrate 1 at a nominal temperature. use, for example at 20 ° C, and preferably less than 150 [Inn, or 100 [Inn. As can be seen in FIG. 7, the charge recovery assembly then comprises a plurality of charge recovery structures, for example floating diffusion nodes 7, each associated with a buried diode 6, and connected together to the same bus 8 to deliver the output signal. For each association between a charge recovery structure and a buried diode 6, a transfer transistor makes it possible to control the transfer of charges from the buried diode to the charge recovery structure. The gates 10 of the transfer transistors are controlled by the same transfer signal TX.
    [0020] FIG. 8 shows another possibility for the read circuit structure, which resumes the configuration of FIG. 7, in which the first type is the N type and the second type is the P type. It should be noted that the same modification can be operated for the configurations exposed with reference to FIGS. 3, 5 and 6. Consequently, the substrate 1 is here of the N type, the first doped region 4 forming with the substrate the injection diode is of the P type, the second With the doped region 6 forming with the substrate, the buried diode is of the P type, the recovery structure has a P-doped region forming the floating diffusion node 7, and the confinement zone 13 is of the N type. In this case, the carriers of the The charges injected by the external photodiode 2 to the substrate 1 are holes, which are then collected by the buried diode and then recovered by the recovery structure. In this FIG. 7, an additional characteristic is indicated by which a second output device 19 is connected to the charge injection branch between the external charge source 2 and the injection diode 4. This second output device 19 comprises an amplifier 26a connected by a selection switch 27a to a multiplexing bus 28a, which may be distinct or confused with the multiplexing bus to which the output device 8 is connected. The input impedance of the amplifier 26a is very large, ideally infinite, equivalent to that of a MOS transistor gate.
    [0021] This second output device 19 allows a reading of the voltage across the injection diode and thus makes it possible to obtain a logarithmic reading of the current generated by the external charge source 2 and injected into the substrate 1, via the exponential relationship. between the voltage and the current flowing from the external charge source 2 to the injection diode. This gives the possibility of a dual reading mode: linear and logarithmic, which improves the dynamics of the read circuit structure since it can respond to both low and high light exposures. However, P-type wafers are more popular in CMOS foundries. In order to be able to realize a pixel reading circuit according to the configuration in which the first type is the N type and the second type is the P type, it is possible to provide the realization of the read circuit structure in a type box. N lightly doped (- LDN-Well "in English for - lightly-doped N-type well"). FIG. 9 shows such an example, with a lightly doped N-type well 14 formed in the P-type substrate 1, in which all of the doped regions mentioned above are formed. The invention is not limited to the embodiment described and shown in the accompanying figures. Modifications are possible, particularly from the point of view of the constitution of the various elements or by substitution of technical equivalents, without departing from the scope of protection of the invention.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. Reading circuit structure, formed on a semiconductor substrate (1) of a first type, for measuring the charges received from a charge source (2) external to the substrate (1) in successive cycles of charge integration, said structure comprising: - an injection diode formed in the substrate (1) by a first PN junction comprising a first doped region (4) of a second type of the substrate (1) for receiving electrical charges of said external source of charge (2), and configured to inject into the substrate (1) the charges received from the external charge source (2), - a collection diode formed in the substrate (1) by a second PN junction comprising a second doped region (6) of the second type buried in the substrate (1) and capable of collecting in the substrate (1) at least a portion of the charges injected by the injection diode and to accumulate these charges during a cycle of integration, - a structure of r charge recovery (7, 15), configured to recover the charges accumulated in said collection diode, - means for initializing the charge recovery structure (7, 15) at the end of each integration cycle, by reducing the electric potential of said charge recovery structure at an initial potential.
    [0002]
    The read circuit structure according to claim 1, wherein the charge recovery structure (7) comprises a floating diffusion node (7) formed by a doped region of the second type in the substrate (1), connected to a output device (8).
    [0003]
    3. reading circuit structure according to the preceding claim, wherein the means for initializing the charge recovery structure comprises an initialization transistor (10) whose gate, electrically isolated from the substrate (1), is located between said node (7) and a reference potential source (VDD), and is adapted to be controlled to bring the potential of said broadcast node (7) to said initial potential.
    [0004]
    4. Read circuit structure according to one of claims 2 or 3, comprising an MOS transfer transistor whose transfer gate (9) is located between said buried diode and said floating diffusion node (7), at above and electrically isolated from the substrate (1), and which is con- nnandable to transfer the collected charges in the second doped region (6) to the floating diffusion node (7).
    [0005]
    A read circuit structure according to any preceding claim, wherein the charge recovery structure comprises - a memory consisting of a doped region (15) of the second type and - a floating diffusion node (7) formed by a doped region of the second type connected to an output device (8), said memory being formed in the substrate (1) between the buried diode and the floating diffusion node (7).
    [0006]
    A read circuit structure as claimed in any one of the preceding claims, wherein an output device (19) is connected between the external charge source (2) and the injection diode to enable voltage reading. at the terminals of the injection diode and thus obtain a logarithmic reading of the current passing between the external charge source (2) and the injection diode.
    [0007]
    A readout circuit structure according to any one of the preceding claims, comprising a confinement zone (13) formed by a doped region of the first type formed in the substrate (1), said confinement zone (13) extending in the depth of the substrate (1) at least opposite the first doped region (4) constituting the injection diode.
    [0008]
    8. reading circuit structure according to the preceding claim, wherein the confinement zone (13) further extends towards the surface of the substrate (1) to the periphery of the injection diode.
    [0009]
    A readout circuit structure according to any one of the preceding claims, comprising a doped region of the first type (12) formed in the substrate (1) surrounding a doped region of the second type (11) of the initialization means, said second type doped region (11) being connected to a reference potential source, and said first type doped region extending to a second type doped region belonging to the charge recovery structure (7).
    [0010]
    The read circuit structure according to any of the preceding claims, wherein the charge recovery assembly comprises a plurality of second doped regions (6) of the second type buried in the substrate (1) each forming a buried diode. with said substrate (1), able to capture in the substrate at least a portion of the charges injected by a common injection diode (4), and to accumulate these charges during a charge integration cycle.
    [0011]
    11. reading circuit structure according to the preceding claim, wherein the injection diode is formed of a plurality of first doped regions of the second type electrically interconnected.
    [0012]
    A read circuit structure according to any one of the preceding claims, wherein the second doped region (6) of the buried collection diode is configured to be fully depleted upon charge transfer to the recovery structure. of loads (7).
    [0013]
    A method of operating a read circuit structure according to any one of the preceding claims, wherein - a first reading of the voltage at the charge recovery structure is made after initialization of said payload structure. recovery of charges and before the transfer of charges from the buried diode to said charge recovery structure, and - a second reading of the voltage at the charge recovery structure is performed after the transfer of charges from the buried diode to said charge recovery structure, the image signal corresponding to the difference between the first reading and the second reading.
    [0014]
    14. A matrix reading circuit comprising a plurality of read circuit structures according to one of claims 1 to 12.35
    [0015]
    15. Hybrid sensor comprising a first substrate on which is formed a read circuit according to the preceding claim, and a second substrate on which is formed a matrix of elements sensitive to electromagnetic radiation constituting the external charge sources (2).
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    同族专利:
    公开号 | 公开日
    CN106415842A|2017-02-15|
    EP3155662A1|2017-04-19|
    CN106415842B|2019-06-14|
    WO2015189359A1|2015-12-17|
    JP2017519375A|2017-07-13|
    US10332926B2|2019-06-25|
    FR3022425B1|2017-09-01|
    US20170213866A1|2017-07-27|
    EP3155662B1|2019-10-23|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1455361A|FR3022425B1|2014-06-12|2014-06-12|CHARGING INJECTION READ CIRCUIT STRUCTURE|FR1455361A| FR3022425B1|2014-06-12|2014-06-12|CHARGING INJECTION READ CIRCUIT STRUCTURE|
    JP2017517412A| JP2017519375A|2014-06-12|2015-06-12|Read circuit structure with charge injection|
    PCT/EP2015/063112| WO2015189359A1|2014-06-12|2015-06-12|Structure of a readout circuit with charge injection|
    CN201580030693.1A| CN106415842B|2014-06-12|2015-06-12|Utilize the structure of the reading circuit of charge injection|
    EP15729435.6A| EP3155662B1|2014-06-12|2015-06-12|Structure of a readout circuit with charge injection|
    US15/316,828| US10332926B2|2014-06-12|2015-06-12|Structure of a readout circuit with charge injection|
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